1. Field of the Invention
The present invention relates to a semiconductor nonvolatile memory device, more particularly to a nonvolatile random-access memory (NVRAM) constituted by a static type random-access memory (SRAM) and an electrically erasable programmable read-only memory (EEPROM).
2. Description of the Related Art
A memory cell unit of an NVRAM includes a cell of the SRAM and a cell of the EEPROM. The SRAM cell is, in general, constituted by a flip-flop circuit having two pairs of transistors and one power source. The EEPROM cell, i.e., the nonvolatile memory cell, is, in general, constituted by a single nonvolatile memory transistor (NV transistor) having a floating gate. The NVRAM cell basically functions as follows. Just before the power source is cut off, the data stored in the SRAM cell is temporarily stored in the EEPROM cell. When power is again supplied, the data stored in the EEPROM cell is recalled to the SRAM cell.
The store and recall operations are performed through the floating gate of the NV transistor. That is, in the store operation, plus or minus charges are injected to the floating gate of the NV transistor so that the NV transistor is set to the ON or OFF state corresponding to the state of the flip-flop circuit of the SRAM. The flip-flop circuit is constituted so there is an unbalance in the channel width and channel length of the load transistors and in the capacitors of the nodes for the purpose of enabling a recall when the NV transistor is turned OFF.
However, there are some problems in establishing such unbalanced states of the channel width and channel length of the transistors and of the capacitors of the nodes in the flip-flop circuit. That is, the memory cell area has to be increased to establish their unbalanced states. It is also difficult to establish precise unbalanced states between capacitors, because other factors of capacity besides expected values arise at the stage of design of the layout of the integrated circuit pattern.